Quad-Core H.264 Encoder

4K60 H.264 encoding with four micro-footprint cores

Quad-Core H.264 Encoder Overview

Quad-Core H.264 Encoder for FPGA's

A2e Quad-Core H.264 Encoder FPGA Core - 4K30 / 4K60

The new A2e Quad-Core H.264 Encoder consists of four H.264 encoder cores along with additional glue logic to support large frame sizes and rates such as 4K60. The Quad-Core H.264 Encoder and updated Linux drivers allow clients to quickly put together a system supporting 4K30 or 4K60 video streams. Encoding image quality, measured by compression ratio, is identical to the original H.264 encoder core.


Quad-Core H.264 Encoder Features

  • 1.5 clocks / 4 pixels processing rate
  • 64-bit DDR memory interface
  • Core clock runs up to 320MHz in a Xilinx XCZU7EV-FFVC1156-2-E
  • Supports resolutions up to 4096 x 4096
  • Generates I and P frames
  • Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
  • Search range: 80 x 48 pixels, Full, 1/2, 1/4 pixel resolution
  • Entropy Encoding: CAVLC
  • Support for intra 4 x 4 DC prediction
  • Support for single or multiple slices via firmware control
  • Supports YUV 4:2:2 video input (converted to 4:2:0; compressed output is always YUV 4:2:0)
  • Fully synchronous design

H.264 Feature Set

  • Supports H.264 Baseline profile
  • Fully compliant with the H.264 specification for encode
  • Both VBR and CBR rate control supported (CBR is software controlled by uP in the core)
  • Search range: 80 x 48 pixels
  • Motion vectors: +/- 32 horizontal, +/- 16 vertical
  • 1/4 pixel resolution
  • Sub-frame latency
  • Maximum number of simultaneous input streams limited only by core throughput

Resource Usage

  • LUT: 45,685
  • FF: 28,708
  • BRAM36: 146
  • DSP: 52

Deliverables

  • H.264 encrypted Verilog net-list (Evaluation versions blank output on a periodic basis)
  • H.264 encrypted RTL model for simulation (ModelSim/Questa compatible)
  • ModelSim/Questa compatible test bench
  • H.264 Encoder User's Manual

C-Model Application

  • C-Model as a Windows program with an easy to use GUI
  • C-Model as a DOS .exe for use with test bench
  • H.264 C-Model DOS User's Manual

Evaluation Design

  • H.264 Evaluation Board User's Manual
  • Complete Vivado FPGA design for Xilinx ZCU106 evaluation board
  • Source for all Linux drivers and BSP
  • Lightweight streaming application to stream compressed video over Ethernet to a video player

Evaluation System

  • Complete redesign of the H.264 Evaluation design
  • Runs on the Xilinx ZCU106 evaluation board
  • No add-on FMC boards required
  • Users can provide YUV files stored on an SD Card for compression by the A2e H.264 Encoder; compressed files are stored back to the SD Card and can be compared to the A2e H.264 C-Model output, allowing verification of the compressed output from the H.264 core against the C-Model

Licensing Options (No Royalties)

  • Evaluation
  • Single Product
  • Unlimited

Get the Data Sheet!

The Data Sheet contains more details on functionality and deliverables. Please email sales to learn more. (sales@A2eTechnologies.com)

Pricing

Please contact us at sales@A2eTechnologies.com for pricing information and any other questions