FPGA core capable of being synthesized in
Altera, Lattice and Xilinx FPGAs. Supports
H.264 variable and fixed bit-rate encoding
of video streams. Encodes video data at 3
clocks/pixel. Typical clock rate in an
Lattice ECP-2 FPGA is 100Mhz. Multiple
cores can be used for processing larger size
or higher bandwidth images. Built in DDR2
memory controller (FPGA vendor
independent). Built in Decoder that can
decode A2e H.264 encoded streams.
Can be bolted on to A2e Image Signal
Processing Pipeline for complete streaming
video solution. Custom versions available.
·
Designed for high-speed,
high-pixel count CMOS sensors
interfacing to medium to high-bandwidth
connections.
·
3 clocks/pixel processing
rate.
·
Built in Decoder that can
decode A2e H.264 encoded streams
(cannot decode H.264 streams from other
encoders)
·
Fully compatible with the
ITU-T H.264 specification.
·
Supports resolutions up to
4096 x 4096 (can be expanded with
additional cores)
· Supports simultaneous
encoding of multiple streams of
arbitrary sizes and compression ratios
·
Generates I and P frames
·
Variable Bit Rate (VBR)
and Constant Bit Rate (CBR)
·
Search range: 80 x 48
pixels, Full, ½, ¼ pixel resolution
·
Entropy Encoding: CAVLC
·
Support for intra 4 x 4 DC
prediction
·
Support for Single or
Multiple slices via firmware control
·
Supports YUV 4:2:0, 4:2:2
video input
·
Fully synchronous design
·
Available as FPGA specific
netlist
Smaller cores can be
created by removing functionality. Examples
are: